JPH0412682Y2 - - Google Patents
Info
- Publication number
- JPH0412682Y2 JPH0412682Y2 JP1987027816U JP2781687U JPH0412682Y2 JP H0412682 Y2 JPH0412682 Y2 JP H0412682Y2 JP 1987027816 U JP1987027816 U JP 1987027816U JP 2781687 U JP2781687 U JP 2781687U JP H0412682 Y2 JPH0412682 Y2 JP H0412682Y2
- Authority
- JP
- Japan
- Prior art keywords
- spacer
- chip
- base
- lead frame
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987027816U JPH0412682Y2 (en]) | 1987-02-26 | 1987-02-26 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1987027816U JPH0412682Y2 (en]) | 1987-02-26 | 1987-02-26 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63136344U JPS63136344U (en]) | 1988-09-07 |
JPH0412682Y2 true JPH0412682Y2 (en]) | 1992-03-26 |
Family
ID=30830201
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1987027816U Expired JPH0412682Y2 (en]) | 1987-02-26 | 1987-02-26 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0412682Y2 (en]) |
-
1987
- 1987-02-26 JP JP1987027816U patent/JPH0412682Y2/ja not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS63136344U (en]) | 1988-09-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS6327860B2 (en]) | ||
US20030124829A1 (en) | Interconnection method entailing protuberances formed by melting metal over contact areas | |
JPS6031102B2 (ja) | 集積回路パツケージおよびその製作方法 | |
JPH0412682Y2 (en]) | ||
JP2668995B2 (ja) | 半導体装置 | |
JPH03196664A (ja) | 半導体素子収納用パッケージ | |
JP3695706B2 (ja) | 半導体パッケージ | |
JPS61121489A (ja) | 基板製造用Cu配線シ−ト | |
JP2548964Y2 (ja) | 半導体素子収納用パッケージ | |
JPS60178655A (ja) | リ−ドフレ−ム | |
JPH0427172Y2 (en]) | ||
JPH0756886B2 (ja) | 半導体パッケージの製造方法 | |
JP2000236034A (ja) | 電子部品用パッケージ | |
JP3176267B2 (ja) | 半導体素子収納用パッケージ | |
JP3051225B2 (ja) | 集積回路用パッケージ | |
JP2866962B2 (ja) | 半導体素子収納用パッケージの製造方法 | |
JP2796178B2 (ja) | 電子部品用ガラス端子 | |
JPS63229843A (ja) | 複合セラミツクス基板 | |
JPH0770634B2 (ja) | セラミツクスパツケ−ジ及びその製造方法 | |
JPS63228741A (ja) | 半導体素子収納用パツケ−ジ | |
JP2703482B2 (ja) | 配線基板 | |
JP2514910Y2 (ja) | 半導体素子収納用パッケージ | |
JPH04266051A (ja) | 半導体素子収納用パッケージの製造方法 | |
JPH0272696A (ja) | セラミックス回路基板 | |
JPH03292761A (ja) | チップキャリヤ |